1. Field of the Invention
The present invention relates to liquid crystal display (LCD) devices. More particularly, the present invention relates to an in plane switching (IPS) mode LCD panel and a method of fabricating the same using a reduced number of mask processes.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices express pictures by selectively altering light transmittance characteristics of liquid crystal material sandwiched between upper and lower substrates. The light transmittance characteristics can be selectively altered by applying an electric field through the liquid crystal material (i.e., driving the liquid crystal material). Depending upon the orientation of the electric field applied through the liquid crystal material, LCD devices may be broadly classified as either a vertical-electric-field-type or a horizontal-electric-field-type LCD device.
LCD devices that drive liquid crystal material using vertically oriented electric fields (e.g., twisted nematic (TN) mode LCD devices) generate electric fields between a pixel electrode formed on the lower substrate and a common electrode formed on the upper substrate. Such LCD devices beneficially have large aperture ratios but display pictures over an undesirably narrow viewing angle of about 90°.
LCD devices that drive liquid crystal material using horizontally oriented electric fields (i.e., in-plane switching (IPS) mode LCD devices) generate electric fields between a pixel electrode and a common electrode formed parallel to each other on the lower substrate. Such IPS mode LCD devices beneficially display pictures over a wide viewing angle of about 160°. Accordingly, a typical IPS mode LCD device includes a lower substrate (i.e., a thin film transistor (TFT) array substrate); an upper substrate (i.e., a color filter array substrate) coupled to, and separated from, the TFT array substrate to form a cell gap; spacers distributed within the cell gap for uniformly maintaining the distance between the TFT and color filter array substrates; and liquid crystal material arranged within the cell gap.
The TFT array substrate includes a plurality of signal wirings for generating a horizontally oriented electric field for each pixel, a plurality of TFTs, and an alignment film coated thereon to impart an alignment to molecules of the liquid crystal material. The color filter array substrate includes a color filter for selectively transmitting light having predetermined ranges of wavelengths, a black matrix for preventing a light from being transmitted in regions outside the pixels, and an alignment film coated thereon to impart an alignment to molecules of the liquid crystal material.
The process used to fabricate the TFT array substrate described above is complicated and relatively expensive because it involves a number of semiconductor processing techniques that require a plurality of mask processes. It is generally known that a single mask process requires many sub-processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, inspection, etc. To reduce the complexity and cost associated with fabricating TFT array substrates, procedures have been developed to minimize the number of masking processes required. Accordingly, a four-mask process has been developed that removes the necessity of a mask process from then standard five-mask process.
FIG. 1 illustrates a plan view of a TFT array substrate of an IPS mode LCD device fabricated using a related art four-mask process. FIG. 2 illustrates a sectional view of the TFT array substrate taken along the I-I′ line shown in FIG. 1.
Referring to FIGS. 1 and 2, the TFT array substrate includes gate lines 2 and data lines 4 formed so as to cross each other on a lower substrate 1 to define a plurality of pixel areas, a TFT 30 provided at each crossing of the gate and data lines 2 and 4, a pixel electrode 22 and a common electrode 84 provided at each pixel area to generate a horizontally oriented electric field, and a common line 86 connected to the common electrode 84. The TFT array substrate further includes a storage capacitor 40 provided at a region where the pixel electrode 22 and the common line 86 overlap, a gate pad 50 connected to each gate line 2, a data pad 60 connected to each data line 4, and a common pad 80 connected to each common line 86.
Each gate line 2 applies a gate signal to a gate electrode 6 of a corresponding TFT 30. Each data line 4 applies a pixel signal to a corresponding pixel electrode 22 via a drain electrode 10 of a corresponding TFT 30. The common lines 86 are oriented parallel to the gate lines 2 and supply a reference voltage to the common electrode 84, enabling the liquid crystal material to be driven.
In response to a gate signal applied from a gate line 2, a TFT 30 charges and maintains a pixel signal, applied to a corresponding data line 4, in the pixel electrode 22. Accordingly, each TFT 30 includes a gate electrode 6 connected to a corresponding gate line 2, a source electrode 8 connected to a corresponding data line 4, and a drain electrode 10 connected to a corresponding pixel electrode 22.
Further, each TFT 30 includes an active layer 14 overlapping the gate electrode 6 and is insulated therefrom by a gate insulating pattern 12. Accordingly, a channel is formed in a portion of the active layer 14 between the source and drain electrodes 8 and 10. An ohmic contact layer 16 is formed on the active layer 14 and ohmically contacts the overlapping data line 4, the source electrode 8, and the drain electrode 10 in addition to an overlaying lower data pad electrode 62 and storage electrode 28.
Each pixel electrode 22 is connected to the drain electrode 10 of a corresponding TFT 30 via a first contact hole 32 formed through a protective film 18. Specifically, the pixel electrode 22 includes a first horizontal part 22a oriented parallel to gate lines 2 and connected to the drain electrode 10, a second horizontal part 22b overlapping the common line 86, and a plurality of finger parts 22c oriented parallel to the common electrode 84 between the first and second horizontal parts 22a and 22b. 
Each common electrode 84 is connected to a corresponding common line 86 and is oriented parallel to the plurality of finger parts 22c. 
Each storage capacitor 40 consists of the common line 86 and the portion of the storage electrode 28 overlapping the common line 86, wherein the two conductors are separated by the gate insulating film 12, the active layer 14, and the ohmic contact layer 16 therebetween. The pixel electrode 22 is connected to the storage electrode 28 via a second contact hole 26 formed through the protective film 18. Constructed as described above, the storage capacitor 40 allows pixel signals charged at the pixel electrode 22 to be uniformly maintained until a next pixel signal is charged at the pixel electrode 22.
Each gate line 2 is connected to a gate driver (not shown) via a corresponding gate pad 50. Accordingly, the gate pad 50 consists of a lower gate pad electrode 52 and an upper gate pad electrode 58. The lower gate pad electrode 52 is an extension of gate line 2 and is connected to the upper gate pad electrode 58 via a third contact hole 54 formed through the gate insulating film 12 and the protective film 18.
Each data line 4 is connected to a data driver (not shown) via a corresponding data pad 60. Accordingly, the data pad 60 consists of a lower data pad electrode 62 and an upper data pad electrode 68. The lower data pad electrode 62 is an extension of the data line 4 and is connected to the upper data pad electrode 68 via a fourth contact hole 64 formed through the protective film 18.
Each common line 86 is connected to an external reference voltage source (not shown) via the common pad 80 to receive a reference voltage. Accordingly, the common pad 80 consists of a lower common pad electrode 82 and an upper common pad electrode 88. The lower common pad electrode 82 is an extension of the common line 86 and is connected to the upper common pad electrode 88 via a fifth contact hole 74 formed through the gate insulating film 12 and the protective film 18.
Generally, a horizontal electric field is generated between the pixel and common electrodes 22 and 84 when a pixel signal is applied from a TFT 30 to a pixel electrode 22 and when a reference voltage is applied from the common line 86 to the common electrode 84. Specifically, the horizontal electric field is formed between the plurality of finger parts 22c of the pixel electrode 22 and the common electrode 84. The liquid crystal molecules have a particular dielectric anisotropy. Therefore, in the presence of the electric field, liquid crystal molecules rotate to align themselves horizontally between the TFT and color filter array substrates and the color filter array substrate. The magnitude of the applied electric field determines the extent of rotation of the liquid crystal molecules. Accordingly, gray scale levels may be displayed by a pixel area by varying the magnitude of the applied electric field.
Having described the TFT array substrate above, a method of fabricating the TFT array substrate according to the related art four-mask process will now be described in greater detail with reference to FIGS. 3A to 3D.
Referring to FIG. 3A, a first conductive pattern group, including the gate line 2, the gate electrode 6, the lower gate pad electrode 52, the common line 86, the common electrode 84, and the lower common pad electrode 82, is formed on the lower substrate 1 in a first mask process.
Specifically, a gate metal layer is formed over the entire surface of the lower substrate 1 in a deposition technique such as sputtering. The gate metal layer typically includes an aluminum-group metal. The gate metal layer is then patterned using photolithography and etching techniques in conjunction with an overlaying first mask pattern to provide the aforementioned first conductive pattern group.
Referring next to FIG. 3B, the gate insulating film 12 is coated over the entire surface of the lower substrate 1 and on the first conductive pattern group. In a second mask process, semiconductor patterns, including the active layer 14 and the ohmic contact layer 16, and a second conductive pattern group, including the data line 4, the source electrode 8, the drain electrode 10, the lower data pad electrode 62, and the storage electrode 28, are provided on the gate insulating film 12.
Specifically, the gate insulating film 12, first and second semiconductor layers, and a data metal layer are sequentially formed over the surface of the lower substrate 1 and on the first conductive pattern group by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and sputtering. The gate insulating film 12 typically includes an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The active layer 14 is formed from the first semiconductor layer and typically includes undoped amorphous silicon. The ohmic contact layer is formed from the second semiconductor layer and typically includes N- or P-doped amorphous silicon. The data metal layer typically includes molybdenum (Mo), titanium (Ti), tantalum (Ta).
A photo-resist film is then formed over the data metal layer and is photolithographically patterned using a second mask pattern. Specifically, the second mask pattern is provided as a diffractive exposure mask having a diffractive exposure region corresponding to a channel portion of a subsequently formed TFT. Upon exposure through the second mask pattern and development, a photo-resist pattern is created wherein a portion of the photo-resist film remaining in a region corresponding to the channel portion has a lower height than portions of the photo-resist film remaining in regions outside the channel portion.
Subsequently, the photo-resist pattern is used as a mask to pattern the data metal layer in a wet etching process and form the aforementioned second conductive pattern group (i.e., the data line 4, the source electrode 8, the drain electrode 10, and the storage electrode 28), wherein the source and drain electrodes 8 and 10 are connected to each other in a region corresponding to the channel portion. Next, the photo-resist pattern is used as a mask to sequentially pattern the first and second semiconductor layers in a dry etching process and form the active layer 14 and the ohmic contact layer 16.
After the active and ohmic contact layers 14 and 16 are formed, the portion of the photo-resist having the relatively lower height is removed from the region corresponding to the channel portion in an ashing process. Upon performing the ashing process, the relatively thicker portions of the photo-resist in regions outside the channel portion are thinned but, nevertheless, remain. Using the photo-resist pattern as a mask, the portion of the second conductive pattern group and the ohmic contact layer 16 arranged in the region corresponding to the channel portion are then etched in a dry etching process. As a result, the active layer 14 within the channel portion is exposed, the source electrode 8 is disconnected from the drain electrode 10, and the remaining photo-resist pattern is removed in a stripping process.
Referring next to FIG. 3C, the protective film 18 is coated over the entire surface of the lower substrate, on the gate insulting film 12, the second conductive pattern group, and the active layer 14. In a third mask process, the first to fifth contact holes 32, 26, 54, 64, and 74, respectively, are formed through the protective film 18.
Specifically, the protective film 18 is formed over the surface of the lower substrate, and on the gate insulting film 12, the second conductive pattern group, and the active layer 14 by a deposition technique such as plasma enhanced chemical vapor deposition (PECVD). The protective film 18 typically includes an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic material having a small dielectric constant such as an acrylic organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane). A third mask pattern is then arranged over the protective film 18 and the protective film 18 is then patterned by using photolithography and etching processes to thereby define the first to fifth contact holes 32, 26, 54, 64, and 74. The first contact hole 32 is formed through the protective film 18 to expose the drain electrode 10, the second contact hole 26 is formed through the protective film 18 to expose the storage electrode 28, the third contact hole 54 is formed through the protective film 18 and the gate insulating film 12 to expose the lower gate pad electrode 52, the fourth contact hole 64 is formed through the protective film 18 to expose the lower data pad electrode 62, and the fifth contact hole 74 is formed through the protective film 18 and the gate insulating film 12 to expose the lower common pad electrode 82.
Referring next to FIG. 3D, a third conductive pattern group including the pixel electrode 22, the upper gate pad electrode 58, the upper data pad electrode 68, and the upper common pad electrode 88 are formed on the protective film 18 in a fourth mask process.
Specifically, a transparent conductive material is coated over the entire surface of the protective film 18 and in the first to fifth contact holes 32, 26, 54, 64, and 74 by a deposition technique such as sputtering. The transparent conductive material typically includes indium-tin-oxide (ITO), tin-oxide (TO), indium-zinc-oxide (IZO) or indium-tin-zinc-oxide (ITZO). In a fourth mask process, the transparent conductive material is patterned using photolithographic and etching techniques to thereby form the aforementioned third conductive pattern group (i.e., the pixel electrode 22, the upper gate pad electrode 58, the upper data pad electrode 68, and the upper common pad electrode 88).
Accordingly, the pixel electrode 22 is electrically connected to the drain electrode 10 via the first contact hole 32 while also being electrically connected to the storage electrode 28, via the second contact hole 26. The upper gate pad electrode 58 is electrically connected to the lower gate pad electrode 52 via the third contact hole 54, the upper data pad electrode 68 is electrically connected to the lower data pad electrode 62 via the fourth contact hole 64, and the upper common pad electrode 88 is electrically connected to the lower common pad electrode 82 via the fifth contact hole 74.
While the TFT array substrate described above may be formed using a four-mask process that is advantageous over previously known five-mask processes, the four-mask process can still be undesirably complicated and, therefore, costly. Accordingly, it would be beneficial to fabricate a TFT array substrate according to a less complex, and therefore less costly, process.